In a large scale semiconductor integrated circuit (hereinafter, referred to as LSI) including a sequential circuit that is operated synchronously with a clock signal, step-out of synchronization of the clock signal (hereinafter, referred to as clock skew) generated by distribution of the clock is considered as a factor for lowering in direct the operation frequency of LSI. With improvement in operation rate of LSI, reduction of clock skew is necessary for realization of high-speed operation of LSI.
Several circuit formats are known as a clock distribution circuit. FIG. 1 shows an H-tree type clock distribution circuit. A tree-type clock distribution represented by the H-tree is known as the circuit to theoretically realize clock skew 0 under the condition that a clock buffer load of each stage is perfectly equalized. However, in actual, it is difficult to realize uniform design of the tree-structure type clocks for all clock synchronization circuits and a clock skew is generated in accordance with fluctuation in the clock buffer driving force and parasitic element of wiring.
Here, it is explained here that the patent documents 1 to 3 (JP-A-Hei6(1994)-260555, JP-A-Hei5(1993)-259414, and JP-A-Hei5(1993)-73167) have been found by searching the related arts from the viewpoint of fishbone clock tree that is realized by arranging in vertical the final stage buffers after the present invention has been obtained. However, in each patent document, the final stage buffers are regularly arranged corresponding to the allowable arrangement of cells.